An earlier related patent application discloses clock gating in the context of a computer system chip with LBIST (logic built in self test) capability. This prior application is commonly assigned with the present application, has an inventor in common herewith, and issued on Sep. 26, 2000 as U.S. Pat. No. 6,125,465, entitled “Isolation/Removal of Faults during LBIST Testing”. The '465 patent is incorporated herein by reference in its entirety. The '465 patent discloses a diagnostic regime under which a clock signal is withheld from a functional unit of a chip which is known to have caused a fault. The remainder of the chip then can be tested to determine if there are further faults in the chip.
The present inventors have recognized that additional testing regimes can be employed using clock gating and/or signal gating.